1. Field of the Invention
The present invention generally relates to emitter coupled logic (ECL) latch circuits, and more particularly to an ECL latch circuit (current switching type) which is suited for use in a high-speed logic circuit of a computer or the like. Particularly, the present invention relates to an ECL latch circuit which requires only a single clock signal.
2. Description of the Related Art
FIG. 1 shows an example of a conventional ECL latch circuit. In FIG. 1, the ECL latch circuit is made up of a data input part 1 and a latch part 2. The data input part 1 includes transistors TR1 through TR4, resistors R1 and R2 and a diode Di. The latch part 2 includes transistors TR5 through TR9 and resistors R3 through R5. V.sub.EE denotes a power source voltage for the current switch, V.sub.TT denotes a power source voltage for the emitter follower end, V.sub.BB denotes a reference voltage, V.sub.CS denotes a constant current control voltage, GND denotes ground, D denotes an input data to the ECL latch circuit, Q denotes an output signal of the ECL latch circuit, CLK denotes a positive clock signal which is applied to a base of the transistor TR5 and CLK denotes a negative clock signal which is applied to a base of the transistor TR1.
A description will be given of an operation of the ECL latch circuit shown in FIG. 1 by referring to FIGS. 2(A) through 2(D). The ECL latch circuit samples the input data D shown in FIG. 2(A) when the negative clock signal CLK shown in FIG. 2(B) is "0" and holds the sampled value when the negative clock signal CLK is "1". When the negative clock signal CLK applied to the transistor TR1 of the data input part 1 is "0", the transistor TR3 turns ON when the input data D is "0". In this state, a low-level collector voltage of the transistor TR3 is applied to a base of the transistor TR9 of the latch part 2. Thus, the level of the output signal Q of the transistor TR9 shown in FIG. 2(D) becomes low and the transistor TR6 turns OFF. The positive clock signal CLK shown in FIG. 2(C) is "1" in this state, and hence the transistor TR5 turns ON and the transistor TR7 turns OFF. When the positive clock signal CLK next changes to "0", the transistors TR5 and TR6 turn OFF, the transistor TR7 turns ON and this state is maintained.
On the other hand, when the negative clock signal CLK applied to the transistor TR1 is "0" and the input data D is "1", the transistor TR2 turns ON and the transistor TR3 turns OFF. In addition, the transistor TR5 is ON because the positive clock signal CLK is "1" in this state, and the transistor TR7 turns OFF. As a result, the output signal Q of the transistor TR9 has a high level and the transistor TR6 is ON. Even when the positive clock signal CLK next changes to "0", the transistor TR7 is maintained in the OFF state because the transistor TR6 is ON.
FIG. 3 shows a bipolar clock driver which is used to generate the positive and negative clock signals CLK and CLK which are applied to the ECL latch circuit shown in FIG. 1.
However, according to the conventional ECL latch circuit, there is a problem in that it is necessary to independently apply the negative clock signal CLK to the data input part 1 and the positive clock signal CLK to the latch part 2. For this reason, it is necessary to use the bipolar clock driver shown in FIG. 3 to generate the required positive and negative clock signals CLK and CLK. Furthermore, a difference is introduced between delay times of the positive and negative clock signals CLK and CLK caused by differences in the lengths of interconnections and capacitances of the interconnections and there is a problem in that this difference in the delay times causes an unstable operation of the ECL latch circuit.
On the other hand, there are scan-in/scan-out type ECL latch circuits which are used for testing logic and control circuits of an integrated circuit. Such a scan-in/scan-out type ECL latch circuit is assembled within an ECL large scale integrated (LSI) circuit, and a value is written in a scan-in mode and a value is read out in a scan-out mode by designating an address.
FIG. 4 shows an example of a conventional scan-in/scan-out type ECL latch circuit. An LSI circuit 11 comprises scan-in/scan-out type ECL latch circuits 12, 13 and 14. A test value is written into each of the latch circuits 12, 13 and 14 via a common scan-in signal line 15. A value is read out from one of the latch circuits 12, 13 and 14 via a common scan-out signal line 16. An address for selecting one of the latch circuits 12, 13 and 14 to which the scan-in is to be made or from which the scan-out is to be made is supplied to the latch circuits 12, 13 and 14 via an address line 17.
While the LSI circuit 11 is operating, the values in the latch circuits 12, 13 and 14 successively change based on the original control or logic function thereof. Mutually different addresses are assigned to the latch circuits 12, 13 and 14. When a scan address is input from the address line 17, one of the latch circuits 12, 13 and 14 which is assigned the same scan address is selected and a value is read out from this one latch circuit and supplied to the scan-out signal line 16. On the other hand, when a test value is input from the scan-in signal line 15, the test value is written into one of the latch circuits 12, 13 and 14 which is selected by the address input from the address line 17. Hence, it is possible to operate the LSI circuit 11 from an arbitrary control or logic state.
FIG. 5 shows a circuit diagram of the scan-in/scan-out type ECL latch circuit shown in FIG. 4. The circuit part shown in FIG. 5 comprises a latch circuit 18, 3-input NOR gates 19 and 20, and decoders 21 and 22. The lower significant bits A0 through A2 of a 6-bit address signal are applied to the decoder 21 while the higher significant bits A3 through A5 of the 6-bit address signal are applied to the decoder 22. A 2-bit latch selection signal is applied to the NOR gate 19, where a bit AD1 of the latch selection signal is obtained from the decoder 21 and a bit AD2 of the latch selection signal is obtained from the decoder 22. The NOR gate 19 is also supplied with a scan-in signal SI. An output signal of the NOR gate 19 is applied to a set terminal S of the latch circuit 18. A reset signal RESET is applied to a reset terminal R of the latch circuit 18. A Q-output signal of the latch circuit 18 is supplied to the NOR gate 20 which is also supplied with the bits AD1 and AD2 of the latch selection signal.
The decoders 21 and 22 respectively convert three bits of the address signal into one of eight possible output signals. A latch selection signal for selecting each of the latch circuits is generated by mutually different combinations of the output signals obtained from the decoders 21 and 22. Sixty-four different latch selection signals can be generated from the 6-bit address signal, and it is thus possible to scan up to sixty-four latch circuits.
When the bits AD1 and AD2 of the latch selection signal are both "0" in FIG. 5, the NOR gates 19 and 20 open and invert the respective signals SI and Q. Hence, a signal SI is output from the NOR gate 19 and a signal Q is output from the NOR gate 20. The signal SI is applied to the set terminal S of the latch circuit 18 and sets the value in the latch circuit 18 to a predetermined value. Before such a signal SI is applied to the set terminal S of the latch circuit 18, all of the latch circuits within the LSI circuit are initialized responsive to the reset signal RESET which is a positive polarity pulse so that the Q-outputs of the latch circuits become "0". The Q-output of the selected latch circuit 18 is output as a scan-out signal SO via the NOR gate 20.
But according to the conventional scan-in/scan-out type ECL latch circuit, two gates are required for each latch circuit because the scan-in signal SI and the scan-out signal SO are gate-controlled. For this reason, there is a problem in that the hardware and cost of the LSI circuit increases considerably with the increase in the number of scan-in/scan-out latch circuits provided within the LSI circuit.
On the other hand, there are ECL master-slave latch circuits constituted by ECL gates. However, when the ECL gates are used to constitute the ECL master-slave latch circuit, the required number of gates becomes considerably large. As a result, there is a limit to the scale of the logic functions which may be realized within one LSI circuit.
FIG. 6 shows an example of a conventional master-slave ECL latch circuit. The master-slave ECL latch circuit is made up of a master latch 31 and a slave latch 32. The master latch 31 includes an OR gate 33, an OR/NOR gate 34, a collector dot AND gate 35 and a NOR gate 36. The slave latch 32 includes NOR gates 37 and 38.
All of the gates 33, 34, 36, 37 and 38 are normal ECL OR/NOR circuits. In addition, the collector dot AND gate 35 can be realized by coupling the collectors of transistors which constitute the AND gate 35.
In FIG. 6, the input data D is supplied to the OR gate 33 of the master latch 31 together with the negative clock signal CLK. The negative clock signal CLK is also supplied to the NOR gate 36 of the master latch 31 and the NOR gate 37 of the slave latch 32. Hence, the master latch 31 enters and samples the value of the input data D when the negative clock signal CLK is "0", and the master latch 31 holds the value "0" when the negative clock signal CLK changes from "0" to "1". On the other hand, the slave latch 32 enters and samples the value of the Q-output of the master latch 31 when the negative clock signal CLK is "1", and the slave latch 32 holds the data SLQ (Q-output signal which is inverted by NOR gate 38) when the negative clock signal CLK changes from "1" to "0".
In other words, when the value of the negative clock signal CLK is "0" and the value of the input data D changes from "0" to "1", the master latch 31 enters and samples the value "1" of the input data D via the AND gate 35, and the master latch 31 holds the value "1" when the negative clock signal CLK changes from "0" to "1". In this state, the Q-output of the master latch 31 output from the OR/NOR gate 34 has a value "0" and is supplied to the NOR gate 38 of the slave latch 32. The output signal SLQ of the slave latch 32 becomes "1" (at this time the negative clock signal CLK is "1" and the input signals of the NOR gate 38 are both "0") and when the negative clock signal CLK changes from "1" to " 0", this value "1" is held in the slave latch 32. The operation is similar when the value of the input data changes from "1" to "0".
FIG. 7 shows another example of a conventional master-slave ECL latch circuit with the scan-in/scan-out function. The master-slave ECL latch circuit shown in FIG. 7 is based on the master-slave ECL latch circuit shown in FIG. 6 and is supplemental with the scan-in/scan-out function. In FIG. 7, those parts which are substantially the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a description thereof will be omitted.
In FIG. 7, a scan-in/scan-out circuit 39 comprises OR/NOR gates 40 and 42, OR gates 41 and 44, and a collector dot AND gate 43 respectively using ECL. In this example, an output signal of the OR gate 44 is not used.
Input data D1 and D2 are supplied to the OR gate 33 of the master latch 31, and the OR/NOR gate 34 can receive a set signal SET. The negative clock signal CLK and a clock enable signal CE are supplied in parallel to the master latch 31 and the slave latch 32.
Latch selection signals AD1 and AD2 which are generated based on the latch address are supplied to the scan-in/scan-out circuit 39. When the latch selection signals AD1 and AD2 are both "0", the scan-in signal SI is supplied to the master latch 31 via the OR gate 41 and the state of the slave latch 32 is read out from the AND gate 43 as a scan-out signal SOUT.
Next, a description will be given of a case where an LSI circuit having such a master-slave ECL latch circuit with the scan-in/scan-out function is tested. For example, a set signal SET having a value "1" is supplied to each of the master-slave ECL latch circuits within the LSI circuit to set the value "1" in all of the master-slave ECL latch circuits. Then, an address of the master-slave ECL latch circuit to be selected is designated and the value of the scan-in signal SI is set to "1" so as to invert the value in the selected master-slave ECL latch circuit to "0". Thereafter, the address of the selected master-slave ECL latch circuit is designated so as to read out the state of the selected master-slave ECL latch circuit as the scan-out signal SOUT. The result of the test is diagnosed based on the scan-out signal SOUT.
But according to the conventional master-slave ECL latch circuit using ECL and the master-slave ECL latch circuit using ECL and having the scan-in/scan-out function, a large number of ECL gates are required and there is a problem in that the scale of the circuit becomes large in order to realize a desired logic function. As a result, in a master slice LSI, the logic functions which may be realized by a predetermined number of gates become limited. This means that the utilization efficiency of the master slice LSI becomes poor and the cost of the LSI circuit increases thereby.